To improve throughput of Electron Beam Direct Writing (EBDW) with Character Projection (CP) method, a structured routing architecture (SRA) has been proposed to restrict VIA placement and wire-track transition. It reduces possible layout patterns in the interconnect layers, and increases VIA and metal figure numbers in the EB shots while suppressing the CP character number explosion. In this paper, we discuss details of the SRA design methodology, and demonstrate the CP performance by SRA in comparison with other EBDW techniques. Our experimental results show viable CP performance for practical use, and prove SRA's feasibility in 14nm mass fabrication.

A 256-bit $mathbb{F}_p$ ECDSA crypto processor featuring low latency, low energy consumption and capability of changing the Elliptic curve parameters is designed and fabricated in SOTB 65nm CMOS process. We have demonstrated the lowest ever reported signature generation time of 31.3 μs at 238MHz clock frequency. Energy consumption is 3.28 μJ/signature-generation, which is same as the lowest reported till date. We have also derived addition formulae on Elliptic curve useful for reduce the number of registers and operation cycles.

An ASIC crypto processor optimized for the 254-bit prime-field optimal-ate pairing over Barreto-Naehrig (BN) curve is proposed. The data path of the proposed crypto processor is designed to compute five Fp2 operations, a multiplication, three addition/subtractions, and an inversion, simultaneously. We further propose a design methodology to automate the instruction scheduling by using a combinatorial optimization solver, with which the total cycle count is reduced to 1/2 compared with ever reported. The proposed crypto processor is designed and fabricated by using a 65nm silicon-on-thin-box (SOTB) CMOS process. The chip measurement result shows that the fabricated chip successfully computes a pairing in 0.185ms when a typical operating voltage of 1.20V is applied, which corresponds to 2.8× speed up compared to the current state-of-the-art pairing implementation on ASIC platform.

We introduce a 16 × cascaded time difference amplifier (TDA) using a differential logic delay cell with 0.18 µm CMOS process. By employing the differential logic delay cell in the delay chain instead of the CMOS logic delay cell, less than 8% TD gain offset with 150 ps input range is achieved. The input referred standard deviation of the output time difference error is 2.7 ps and the input referred is improved by 17% compared with that of the previous TDA using the CMOS logic delay cell.

We present a 3-D range map acquisition system using a gray-encoded time-multiplexing structured pattern. In this method the only information needed to reconstruct 3-D range map is whether the pixel is bright or not for the exposed structured patterns. A dedicated image sensor to capture the pattern consists of pixel parallel 1-bit A/D converter, in-pixel pattern address memory and column parallel digital pattern address readout circuit. This in-pixel memory and digital bit-parallel pattern address readout eliminate unnecessary readout of pattern data to enhance 3-D acquisition speed. We fabricated the image sensor in 0.18 µm CMOS and demonstrated up to 122 range map per second 3-D range map acquisition performance for 7 patterns with the average error of 3.2 mm under the condition of 10% pattern recognition error.

In this paper, we propose a register file with data bypassing function. This register file bypasses data using data bypassing units instead of functional units when actual operation in functional units such as ALU is unnecessary. Applying this method to a general purpose microprocessor with benchmark programs, we demonstrate 50% power consumption reduction in functional units. Though length of bus lines increases a little due to an additional hardware in register file, as buses are not driven when data is bypassed, power consumption in bus lines is also reduced by 40% compared with the conventional architecture.

This paper proposes a time-to-digital converter (TDC) utilizing the cascaded time difference amplifier (TDA) and shows measurement results with 0.18 µm CMOS. The proposed TDC operates in two modes, a wide input range mode and a fine time resolution mode. We employ a non-linearity calibration technique based on a lookup table. The wide input range mode shows 10.2 ps time resolution over 1.3 ns input range with DNL and INL of +0.8/-0.7LSB and +0.8/-0.4LSB, respectively. The fine time resolution mode shows 1.0 ps time resolution over 60 ps input range with DNL and INL of +0.9/-0.9LSB and +0.8/-1.0LSB, respectively.

This paper demonstrates an autonomous di/dt control of power supply for margin aware operation. A di/dt on the power line is detected by a mutual inductor, the induced voltage is multiplied by Gilbert multiplier and the following low pass filter outputs a DC voltage in proportion to the di/dt. The DC voltage is compared with reference voltages, and the modes of the internal circuit is controlled depending on the comparators output. By using this scheme, the di/dt noise power can be autonomously controlled to fall within a defined range set by the reference voltages. Our experimental results show that the internal circuit oscillates between the all-active and the half-active modes, also show that the all/half ratio and the oscillation frequency changes depending on the reference voltages. It proves that our autonomous di/dt noise control scheme works as being designed.

In this paper, we present a pixel-level color image sensor with efficient ambient light suppression using a modulated RGB flashlight to support a recognition system. The image sensor employs bidirectional photocurrent integrators for pixel-level demodulation and ambient light suppression. It demodulates a projected flashlight with suppression of an ambient light at short intervals during an exposure period. In the imaging system using an RGB modulated flashlight, every pixel provides innate color and depth information of a target object for color-based categorization and depth-key object extraction. We have designed and fabricated a prototype chip with 6464 pixels using a 0.35 µm CMOS process. Color image reconstruction and time-of-flight range finding have been performed for the feasibility test.

The Internet of Things (IoT) implicates an infrastructure that creates new value by connecting everything with communication networks, and its construction is rapidly progressing in anticipation of its great potential. Enhancing the security of IoT is an essential requirement for supporting IoT. For ensuring IoT security, it is desirable to create a situation that even a terminal component device with many restrictions in computing power and energy capacity can easily verify other devices and data and communicate securely by the use of public key cryptography. To concretely achieve the big goal of penetrating public key cryptographic technology to most IoT end devices, we elaborated the secure cryptographic unit (SCU) built in a low-end microcontroller chip. The SCU comprises a hardware cryptographic engine and a built-in access controlling functionality consisting of a software gate and hardware gate. This paper describes the outline of our SCU construction technology's research and development and prospects.

This paper presents a new high-speed and area-efficient dual-rail PLA. The proposed circuit includes three schemes: 1) a divided column scheme (DCS), 2) a programmable sense-amplifier activation scheme (PSAS), and 3) an interdigitated column scheme (ICS). In the DCS, a column circuit of a PLA is divided and each circuit operates in parallel. This enhances the performance of the PLA, and this scheme becomes more effective as input data bandwidth increases. The PSAS is used to generate an activation pulse for sense amplifiers in the PLA. In this scheme, the proposed delay generators enable to minimize a timing margin depending on process variations and operating conditions. The ICS is used to enhance the area-efficiency of the PLA, where a method of physical compaction is employed. This scheme is effective for circuits which have the regularity in logic function such as arithmetic circuits. As applications of the proposed PLA, a comparator, a priority encoder, and an incrementor for 128-bit data processing were designed. The proposed circuit design schemes achieved a 22.2% delay reduction and a 37.5% area reduction on average over the conventional high-speed and low-power PLA in a 0.13-µm CMOS technology with a supply voltage of 1.2 V.

In this paper, a high-speed PLA based on dynamic array logic circuits with latch sense amplifiers is presented. The present circuit consists of logic cell arrays, dual-rail bit-lines, latch sense amplifiers, and control blocks. By using a charge sharing scheme and latch sense amplifiers, voltage swings of the bit-lines are reduced compared to the conventional circuits, thus a high-speed and low-power operation is achieved. The present array logic configuration can realize any logic function expressed in the sum-of-products form by using PLA structure. As an application of the proposed PLA, a 32-bit binary comparator is designed and implemented in a 0.6-µm double-poly triple-metal CMOS process. Results of HSPICE simulation show a better performance compared to the conventional circuits. Functional testing using electron beam probing shows that the present circuit operates correctly.

This paper proposes a deep neural network named BayesianPUFNet that can achieve high prediction accuracy even with few challenge-response pairs (CRPs) available for training. Generally, modeling attacks are a vulnerability that could compromise the authenticity of physically unclonable functions (PUFs); thus, various machine learning methods including deep neural networks have been proposed to assess the vulnerability of PUFs. However, conventional modeling attacks have not considered the cost of CRP collection and analyzed attacks based on the assumption that sufficient CRPs were available for training; therefore, previous studies may have underestimated the vulnerability of PUFs. Herein, we show that the application of Bayesian deep neural networks that incorporate Bayesian statistics can provide accurate response prediction even in situations where sufficient CRPs are not available for learning. Numerical experiments show that the proposed model uses only half the CRP to achieve the same response prediction as that of the conventional methods. Our code is openly available on https://github.com/bayesian-puf-net/bayesian-puf-net.git.

BLS signature is an elliptic curve cryptography with an attractive feature that signatures can be aggregated and shortened. We have designed two ASIC architectures for hashing to the elliptic curve and pairing to minimize the latency. Also, the designs are optimized for BLS12-381, a relatively new and safe curve.